A microelectronic package commonly includes one or more Redistribution Layers (RDLs) over which a Ball Grid Array (BGA) is produced. The RDLs contain electrically-conductive interconnect lines, which electrically couple the BGA solder balls to the microelectronic device or devices (e.g., semiconductor die) contained within the package. The interconnect lines are defined by patterning one or metal levels, which are interspersed with alternating dielectric layers. A microelectronic package can contain a single patterned metal level or, possibly, five or more metal levels depending upon the wiring complexity of the package. The final or outermost metal level is typically patterned to include flat solder pads joined to the interconnect lines. A solder mask layer is deposited over the last metal level, and openings are formed in the solder mask layer to expose the solder pads. The BGA solder balls are then deposited in the solder mask openings and contact the solder pads. Heat treatment is carried-out to reflow the BGA solder balls such that solder joints are formed between the solder balls and the underlying solder pads. Fabrication of the microelectronic package can then be completed by, for example, singulation of a panel or wafer containing the microelectronic package. A secondary solder reflow process may also be carried-out when the microelectronic package is mounted to a larger system or device, such as a Printed Circuit Board (PCB).
Fabrication processes of the type described above typically produce solder joints of at least moderate mechanical strength, which is adequate for most applications. However, the mechanical strength of the solder joints formed between the solder pads and the BGA solder balls can be undesirably limited in certain instances, such as when a microelectronic package is subject to high impact loads or to significant vibratory forces during usage. Considering this, it is desirable to provide microelectronic packages and methods for fabricating microelectronic packages having enhanced solder joint strength and reliability. Ideally, embodiments of such a fabrication method could be utilized to produce various different types of microelectronic packages, such as Fan-In Wafer Level Packages (FI-WLPs) and Fan-Out Wafer Level Packages (FO-WLPs), with relatively few additional processing steps to minimize manufacturing time, cost, and complexity. Other desirable features and characteristics of the present invention will become apparent from the subsequent Detailed Description and the appended Claims, taken in conjunction with the accompanying Drawings and the foregoing Background.
For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the exemplary and non-limiting embodiments of the invention described in the subsequent Detailed Description. It should further be understood that features or elements appearing in the accompanying figures are not necessarily drawn to scale unless otherwise stated. For example, the dimensions of certain elements or regions in the figures may be exaggerated relative to other elements or regions to improve understanding of embodiments of the invention.